1. Field of the Invention
The present invention relates to semiconductor devices, mask ROMs and fabrication methods therefor. More particularly, the invention relates to semiconductor devices in which the device isolation is achieved without utilizing LOCOS films, and mask ROMs incorporating such semiconductor devices in peripheral circuitry thereof. The invention further relates to fabrication methods for such semiconductor devices and mask ROMs.
2. Description of Related Art
In MOS devices, device isolation is achieved by utilizing PN junction and/or low dielectric film. This device isolation technology is employed to prevent a reduction in the breakdown voltage of a device due to punch-through and the channel formation of a parasitic transistor caused by gate interconnection or metallization.
As shown in FIG. 17, a conventional mask ROM includes a memory cell array (flat cell) M employing PN junction isolation and a peripheral circuitry C employing LOCOS isolation film 47. With reference to FIG. 17, a method for fabricating the conventional mask ROM will be described.
An N-well 41 and a P-well 42 each having a surface impurity concentration of about 1.times.10.sup.17 /cm.sup.3 are formed in a silicon substrate 40. An oxide film and a silicon nitride film are then formed on an entire surface of the silicon substrate 40. A resist pattern having a window on a region in which an LOCOS film is to be formed is formed on the substrate 40 by conventional photolithography and etching techniques. The silicon nitride film is patterned by using the resist pattern as a mask.
After the resist pattern is removed, a resist pattern is formed on the substrate 40 so as to cover only the N-well 41. By using the resist pattern and the silicon nitride film as masks, boron ions are implanted into the silicon substrate 40 in a dose of about 7.times.10.sup.13 /cm.sup.2 at an implantation energy of about 15 KeV to form a channel stopper just below the region provided for the LOCOS film formation.
After the resist pattern is removed, pyrolytic oxidation is carried out at a temperature of about 950.degree. C. by using the silicon nitride film as a mask to form LOCOS film 47 having a thickness of about 600 nm. At this time, channel stopper 48 is formed just below the LOCOS film 47 in the P-well 41.
In turn, the silicon nitride film is removed by using hot phosphoric acid. A resist pattern is formed to cover the N-well 41, and then boron ions are implanted into the substrate in a dose of about 2.5.times.10.sup.12 /cm.sup.2 at an implantation energy of 20 KeV by using the resist pattern as a mask to adjust the threshold voltage of an N-channel transistor to be formed in the N-well 42.
After the resist pattern is removed, a resist pattern is formed to cover the P-well 42, and then boron ions are implanted into the substrate in a dose of about 3.times.10.sup.12 /cm.sup.2 at an implantation energy of about 20 KeV to adjust the threshold voltage of a P-channel transistor to be formed in the N-well 41. In turn, the resist pattern is removed, and arsenic ions are implanted into the substrate masked with another resist pattern in a dose of about 2.0.times.10.sup.15 /cm.sup.2 at an implantation energy of about 40 KeV. After the resist pattern is removed, the substrate is annealed at a temperature of about 900.degree. C. for about 30 minutes to achieve diffused bit line connections in the memory cell array M.
In turn, a gate electrode 52 is formed by conventional process. The substrate 40, which is masked with a photoresist in the peripheral circuitry C and with the gate electrode 52 in the memory cell array M, is implanted with boron ions in a dose of about 3.times.10.sup.13 /cm.sup.2 at an implantation energy of about 20 KeV to form junction isolation for isolating the diffused bit line connections from each other.
After removing the photoresist, an oxide film is deposited to a thickness of about 250 nm, and etched back for the formation of spacers 55 on sidewalls of the gate electrode 52. With photoresists for respectively masking the N-well 41 and the P-well 42, a P.sup.+ diffusion layer 56 and an N.sup.+ diffusion layer 57 are formed in the peripheral circuitry C.
In turn, boron ions are implanted into desired channel regions in the memory cell array in a dose of about 2.times.10.sup.14 /cm.sup.2 at an implantation energy of about 180 KeV by using a photoresist as a mask for the programming of the ROM. Thus, transistors having a high threshold voltage are formed.
After the photoresist is removed, interlayer insulation films 60 and 61, contact holes and metal wiring 62 are formed by conventional processes. Thus, the mask ROM is completed.
As can be understood from the foregoing, the process of the LOCOS isolation in the peripheral circuitry C of the mask ROM occupies about 10% to about 15% of the overall mask ROM production process, and takes three to four days, resulting in prolonged production period and costly production. Further, the LOCOS isolation roughens the substrate surface. This hinders microfabrication and thereby results in a reduced yield.
To cope with this problem, U.S. Pat. No. 4,458,262 proposes a device isolation method based on junction isolation. This method is implemented as follows.
As shown in FIG. 18, an N.sup.+ diffusion layer 71 is formed in a P-type silicon substrate 70. Then, a photoresist 72 is formed on the substrate 70, and boron ions are implanted into the substrate masked with the photoresist 72 in a dose of about 2.times.10.sup.14 /cm.sup.2 to form a P.sup.+ diffusion layer 73, as shown in FIG. 19. After the photoresist 72 is removed as shown in FIG. 20, the substrate is subjected to a heat treatment for the activation of the impurities and for the recovery of the crystallinity of the silicon substrate 70 and, thus, the junction isolation is achieved.
The aforesaid PN junction isolation suppresses the reduction in the withstand voltage due to punch-through between diffused bit lines, and prevents the channel inversion of a parasitic transistor which would otherwise be caused by metal wiring. However, a gate insulation film formed in a region just below a gate electrode where the channel inversion of a parasitic transistor should be prevented is very thin. Therefore, the channel inversion of the parasitic transistor caused by the gate electrode cannot be prevented with a presently utilized level of impurity concentration in the well or in the PN junction isolation. Accordingly, the PN junction isolation cannot be employed for the device isolation in the peripheral circuitry.
The PN junction isolation is required to have a high impurity concentration for the prevention of the channel inversion of the parasitic transistor caused by the gate electrode. The gate electrode disposed in contact with the diffusion layer, however, leads to an increase in the junction capacitance and a reduction in the junction breakdown voltage.
For example, the junction breakdown voltage decreases with increasing impurity concentration at a PN junction isolation surface, as shown in FIG. 3. Therefore, where the impurity concentration at the PN junction isolation surface is higher than about 3.times.10.sup.17 /cm.sup.3 in a device operable at a voltage of 5 V, it is impossible to provide a junction breakdown voltage of higher than 6 V. To ensure a junction breakdown voltage of at least 6 V while allowing the PN junction isolation to have a relatively high surface impurity concentration, e.g., 1.times.10.sup.18 /cm.sup.3, the PN junction isolation should be spaced apart from the diffusion layer by not less than 0.4 .mu.m, as shown in FIG. 21. In consideration of a necessary overlap margin and the lateral diffusion of impurity from the junction isolation, the spacing between the PN junction isolation and the diffusion layer should be not less than 0.6 .mu.m as shown in FIG. 22. This leads to limited microfabrication of the device.